Workshop on Application Specific Processors

Thursday, October 4

8:30 - Introduction

8:45 - 10:45 Session 1: Compiler Technology

"Compiler-Driven Reconfiguration of Multiprocessors"
Michael Hussmann, Michael Thies, Uwe Kastens, Madhura Purnaprajna, Mario Porrmann, Ulrich Ruckert; Computer Science, U Paderborn

"Pipeline Exploration for Reconfigurable Targets"
Kieron Turkington, George A. Constantinides, Konstantinos Masselos, Peter Y.K. Cheung; Imperial College London

"Data Reuse Exploration for Low Power Reconfigurable Systems"
Qiang Liu, George A. Constantinides, Konstantinos Masselos and Peter Y.K. Cheung; Imperial College London

"Power Conscious Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm"
Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Yunheung Paek

10:45 - 11:00 Break

11:00 - 12:30 Special Session: RASP in WASP: Real Application-Specific Processors
Organized by Grant Martin, Tensilica; Session Moderator - Ahmed Jerraya of CEA, Grenoble

Session participants:

Mike Lewis, Principal, Feature phone system engineering, Infineon,
"ASPs for mobile connectivity products"

Jean-Michel Moutin, IP, Subsystem and Infrastructure Architecture Manager - Home Video Division, STMicroelectronics,
"Usage of Extensible Cores in Home Video Products : does it fit ?"

Phil Young, Chief Scientist - Digital Systems, NemeriX SA,
"Optimizing GNSS chipset design using ASIP technology"

12:30 - 2:00p Lunch

2:00p - 3:30p Session 2: Design Methodologies and Architectures

"Efficient Resource Utilization for an Extensible Processor through Dynamic Instruction Set Adaptation"
Lars Bauer, Muhammad Shafique, Joerg Henkel; CES, University of Karlsruhe

"An Architecture Description Language for Coarse-grained Reconfigurable Arrays"
Julio Oliveira Filho, Stephan Masekowsky, Thomas Schweizer, Wolfgang Rosenstiel, University Tuebingen

"Exploration of Alternative Topologies for Application-Specific 3D Networks-on-Chip"
Alexandros Bartzas, Nikolaos Skalis and Dimitrios Soudris; Democritus University of Thrace, Greece

3:30p - 3:45p Break

3:45p - 4:45p Keynote: Chris Rowen, CEO, Tensilica: "Processors and Unified SOC Design"

4:45p - 5:00p Break

5:00p - 6:30p Session 3: Real-Time and System Software

"Application-Driven Register File Mapping for Rapid Task Preemption in Real-Time Multi-Tasked Embedded Systems"
Xiangrong Zhou, Peter Petrov; ECE, University of Maryland, College Park

"A Specialized and Predictable Processor for Real-time Systems"
Arnaldo S. R. Oliveira, Luis Almeida, Antonio Ferrari; Universidade de Aveiro, Campus Universitario de Santiago

"P2V: An Architecture for Zero-Overhead Online Verification of Software Programs"
Hong Lu, Alessandro Forin; Microsoft Research

Friday, October 5

8:30 - 9:30 Invited Talk - Sanjay Patel, AGEIA Technologies and UIUC: "AGEIA PhysX: An ASIC Architecture for Real-time, Interactive Physics"

9:30-9:45 Break

9:45 - 11:45 Session 4: Applications

"A Packet Classification Technique for On-Chip Processing Path Selection"
Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf; Technische Universitaet Muenchen

"Server I/O Acceleration Using an Embedded Multi-core Architecture"
Lurng-Kuo Liu, Fei Chen, Christos J. Georgiou, Guang R. Gao; IBM Corporation

"A VLIW Vector Media Coprocessor Architecture with Cascaded SIMD ALUs"
Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, and Masaki Nakagawa; Toshiba Corporation Semiconductor Company

"Design exploration for an Ogg/Vorbis decoder for VLIW architectures"
Federico Ferrari and Erick Amador; University of Lugano, ALaRI institute

WASP, 2002

WASP, 2003

WASP, 2004

WASP, 2005